1、CS4100: 計算機結構Designing a Multicycle Processor,國立清華大學資訊工程學系 九十五學年度第一學期 Adapted from class notes of D. Patterson and W. Dally Copyright 1998, 2000 UCB,Multicycle Design-2,Outline,Designing a processor Building the datapath A single-cycle implementation A multicycle implementation Microprogramming: sim 。

2、plifying control (Appendix C.4) Exceptions,Multicycle Design-3,Recap: A Single-Cycle Processor,CPI=1,Multicycle Design-4,PC,Inst Memory,mux,ALU,Data Mem,mux,PC,Reg File,Inst Memory,mux,ALU,mux,PC,Inst Memory,mux,ALU,Data Mem,PC,Inst Memory,cmp,mux,Reg File,Reg File,Reg File,Arithmetic memory needs r 。

3、ead signal PC and A to one ALU input;
four sources to another input,Fig. 5.27,Multicycle Design-11,Adding Branch/Jump,Three sources to PC Two PC write signals,Fig. 5.28,Multicycle Design-12,Outline,Designing a processor Building the datapath A single-cycle implementation A multicycle implementation。

4、Multicycle datapath Multicycle execution steps Multicycle control (Appendix C.3) Microprogramming: simplifying control (Appendix C.4) Exceptions,Multicycle Design-13,Instruction Fetch Instruction Decode and Register Fetch Execution, Memory Address Computation, or Branch Completion Memory Access or R 。

5、-type Instruction Completion Memory Read Completion (Write-back)INSTRUCTIONS TAKE FROM 3 - 5 CYCLES,Five Execution Steps,Multicycle Design-14,Step 1: Instruction Fetch,Use PC to get instruction and put it in the Instruction Register (IR) Increment the PC by 4 and put the result back in the PC Can be 。

6、 described succinctly using RTL (Register-Transfer Language)IR = MemoryPC;
PC = PC + 4;
Can we figure out the values of the control signals?What is the advantage of updating the PC now,Multicycle Design-15,Step 2: Instruction Decode and Register Fetch,Read registers rs and rt in case needed Compute th 。

7、e branch address in case the instruction is a branch RTL:A = RegIR25-21;
B = RegIR20-16;
ALUOut=PC+(sign-ext(IR15-0)2);
We arent setting any control lines based on the instruction type yet(we are busy decoding it in control logic,Multicycle Design-16,ALU is performing one of three functions, based on。

8、instruction type: Memory Reference:ALUOut = A + sign-extend(IR15-0);
R-type:ALUOut = A op B;
Branch:if (A=B) PC = ALUOut,Step 3: Execution,Multicycle Design-17,Loads and stores access memoryMDR = MemoryALUOut;
orMemoryALUOut = B;
R-type instructions finishRegIR15-11 = ALUOut;
The write actually takes。

9、place at the end of the cycle on the edge,Step 4: R-type or Memory-access,Multicycle Design-18,Loads write to register RegIR20-16= MDR;
What about all the other instructions,Step 5: Write-back,Multicycle Design-19,Summary of the Steps,Fig. 5.30,Multicycle Design-20,Cycle 1 of add,IR = MemoryPC;
PC =。

10、PC + 4,Multicycle Design-21,Cycle 2 of add,A=RegIR25-21;
B=RegIR20-16;
ALUOut=PC+(sign-ext(IR15-0)2,Multicycle Design-22,Cycle 3 of add,ALUOut = A op B,Multicycle Design-23,Cycle 4 of add,RegIR15-11 = ALUOut,Multicycle Design-24,How many cycles will it take to execute this code? lw $t2, 0($t3)lw $t3 。

11、, 4($t3)beq $t2, $t3, Labeladd $t5, $t2, $t3sw $t5, 8($t3)Label:. What is going on during the 8th cycle of execution? In what cycle does the actual addition of $t2 and $t3 takes place,Simple Question,assume not,Multicycle Design-25,Outline,Designing a processor Building the datapath A single-cycle i 。

12、mplementation A multicycle implementation Multicycle datapath Multicycle execution steps Multicycle control (Appendix C.3) Microprogramming: simplifying control (Appendix C.4) Exceptions,Multicycle Design-26,Implementing the Control,Value of control signals is dependent upon: what instruction is bei 。

【CS4100|CS4100： 计算机结构】13、ng executed which step is being performed Control must specify both the signals to be set in any step and the next step in the sequence Control specification Use a finite state machine (graphically) Use microprogramming Implementation can be derived from the specification and use gates, ROM, or PLA, 。

14、Multicycle Design-27,Several possible initial representations, sequence control and logic representation, and control implementation = all may be determined indep.Initial Rep. Finite State Diagram Microprogram Sequencing Explicit Next State Microprogram Control Function Counter + Dispatch ROMs Logic 。

15、 Rep. Logic Equations Truth Tables Implementation PLA ROM,Controller Design: An Overview,hardwired control,microprogrammed control,Multicycle Design-28,Finite state machines: a set of states and next state (set by current state and input) output (set by current state and possibly input) We will use。

16、a Moore Machine (output based only on the current state,Review: Finite State Machines,Multicycle Design-29,Control State,Next State Logic,Output Logic,inputs (conditions,outputs (control points,State X,Register Transfer Control Points,Depends on Input,State specifies control points for RT Transfer a 。

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标题：CS4100|CS4100： 计算机结构