『易坊知识库摘要_CS4100|CS4100： 计算机结构( 二 )』17、t exiting state (same falling edge) One state takes one cycle,Our Control Model,Multicycle Design-30,Summary of the Steps,Fig. 5.30,Control Specification for Multicycle,IR = MEMPC PC = PC + 4,A =...

17、t exiting state (same falling edge) One state takes one cycle,Our Control Model,Multicycle Design-30,Summary of the Steps,Fig. 5.30,Control Specification for Multicycle,IR = MEMPC PC = PC + 4,A = Rrs B = Rrt S = PC+sx(Imm16)|00,PC = IR,R-type,S = A op B,Rrd = S,S = A + sx(Imm16,Rrt = M,M = MEMS,lw/s 。

18、w,If zero PC = S,jump,beq,Instruction fetch,Decode/register fetch,Execute,Memory access,Memory read,MEMS = B,lw,sw,Multicycle Design-32,Organization of Multicycle Processor,Fig. 5.28,Multicycle Design-33,Control Signals,Signal nameEffect when deassertedEffect when assertedALUSrcA1st ALU operand = PC 。

19、1st ALU operand = RegrsRegWriteNoneReg file is written MemtoRegReg. data input = ALUReg. write data input = MDR RegDstReg. write dest. no. = rtReg. write dest. no. = rdMemReadNoneMemory at address is readMemWriteNoneMemory at address is written IorDMemory address = PCMemory address = ALUoutIRWriteNo 。

20、neIR = MemoryPCWriteNonePC = PCSourcePCWriteCondNoneIf zero then PC = PCSource Signal nameValueEffect ALUOp00ALU adds 01ALU subtracts 10ALU operates according to func codeALUSrcB002nd ALU input = B 012nd ALU input = 4 102nd ALU input = sign extended IR15-0 112nd ALU input = sign ext., shift left 2 I 。

21、R15-0PCSource00PC = ALU (PC + 4) 01PC = ALUout (branch target address) 10PC = PC+431-28 : IR25-0 2,Single Bit Control,Multiple Bit Control,Fig. 5.29,Multicycle Design-34,Mapping RT to Control Signals,Instruction fetch and decode portion of every instruction is identical,Fig. 5.32,A = Rrs B = Rrt S = 。

22、 PC+ sx(Imm16)|00,IR = MEMPC PC = PC + 4,Multicycle Design-35,Mapping RT to Control Signals,FSM for controllingmemory referenceinstructions,Fig. 5.33,Complete FSM,Fig. 5.38,State number assignment,Multicycle Design-37,input output op SDatapath control NS 000000 0000100101000000100 0001 000000 000100 。

23、0000000011000 0110 000000 0010000000000010100 xxxx 000000 1010 000000 1111 000001 0000 000010 0000 100101000000100 0001 000010 0001 000000000011000 1001 000000 0010 000000000010100 xxxx,Truth Table,Multicycle Design-38,From FSM to Truth Table,Please reference the logic equations in Fig. C.3.3 and th 。

24、e truth table in Fig. C.3.6,OutputEquation PCWritestate0 + state9 PCWriteCondstate8 IorDstate3 + state5 NextState0state4 + state5 + state7 + state8 +state9 NextState1state0 NextState2state1 (op = lw) + (op = sw) NextState3state2 (op = lw),OutputCurrent states 0 1 2 3 4 5 6 7 8 9 PCWrite1 0 0 0 0 0 0 。

25、 0 0 1 PCWriteCond0 0 0 0 0 0 0 0 1 0 IorD0 0 0 1 0 1 0 0 0 0,Multicycle Design-39,state,6,4,11,next state,op,zero,control points,state,op,cond,next state,control points,Truth Table,datapath state,Control signals,Designing FSM Controller,Multicycle Design-40,The Control Unit,Fig. C.3.2,Sequence Cont 。

26、rol,Multicycle Design-41,PLA Implementation,Fig. C.3.9,Sequence Control,Multicycle Design-42,Need a ROM of 10-bit address, 20-bit word (16-bit datapath control, 4-bit next state) Address ROM content op SDatapath control NS 000000 0000100101000000100 000000 0001000000000011000 000000 0010000000000010 。

27、100 000000 1010 000000 1111 000001 0000 000010 0000 100101000000100 000010 0001 000000000011000 000000 0010 000000000010100,ROM Implementation,0001,Multicycle Design-43,Address ROM content op SDatapath control NS 000000 0000100101000000100 0001 000000 0001000000000011000 0110 000000 0010000000000010 。

28、100 xxxx 000000 1010 000000 1111 000001 0000 000010 0000 100101000000100 0001 000010 0001 000000000011000 1001 000000 0010 000000000010100 xxxx,ROM Implementation(Truth Table,Rather wasteful, since for lots of entries, outputs are same or are dont-care Could break up into two smaller ROMs (Fig. C.3. 。

29、7, C.3.8,Multicycle Design-44,ROM vs PLA,ROM: use two smaller ROMs (Fig. C.3.7, C.3.8) 4 state bits give the 16 outputs, 24x16 bits of ROM 10 bits (op + state) give 4 next state bits, 210 x 4 bits of ROM Total = 4.3K bits of ROM (compared to 210 x 20 bits of single ROM implementation) PLA is much sm 。

30、aller can share product terms only need entries that produce an active output can take into account dont-cares Size is (#inputs #product-terms) + (#outputs #product-terms) For this example = (10 x17)+(20 x17) = 460 PLA cells PLA cells usually about the size of a ROM cell (slightly bigger,Complete FS 。

31、M,Fig. 5.38,State number assignment,Multicycle Design-46,Use Counter for Sequence Control,Fig. C.4.1,No Next-State Lines,Multicycle Design-47,Address Select Unit,AddrCtl Value: 0Set state to 0 1Dispatch ROM 1 2Dispatch ROM 2 3Use incrementedstate,Fig. C.4.2,Control Contents,Fig. C.4.3, C.4.4,Multicy 。

32、cle Design-49,Outline,Designing a processor Building the datapath A single-cycle implementation A multicycle implementation Multicycle datapath Multicycle execution steps Multicycle control Microprogramming: simplifying control (Appendix C.4) Exceptions,Multicycle Design-50,Several possible initial。

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标题：CS4100|CS4100： 计算机结构( 二 )