49、 vs. disk sectors virtual memory vs. physical memory protects each user program from others Exceptions allow the system to take action in response to events that occur while user program is executing OS begins at the handler,User/System Modes,Multicycle Design-69,Two Types of Exceptions,Interrupts:。

50、caused by external events and asynchronous to execution= may be handled between instructions simply suspend and resume user program Exceptions: caused by internal events and synchronous to execution, e.g., exceptional conditions (overflow), errors (parity), faults instruction may be retried or simul 。

51、ated and program continued or program may be aborted,Multicycle Design-70,MIPS Convention of Exceptions,MIPS convention: exception means any unexpected change in control flow, without distinguishing internal or external use interrupt only when the event is externally caused Type of eventFrom where?M 。

52、IPS terminologyI/O device requestExternalInterruptInvoke OS from user programInternalExceptionHardware malfunctionsEitherException orInterruptArithmetic overflow InternalExceptionUsing an undefined inst.InternalException,Multicycle Design-71,Precise Interrupts,Precise: machine state is preserved as。

53、if program executed upto the offending inst. Same system code will work on different implementations of the architecture Position clearly established by IBM, and taken by MIPS Difficult in the presence of pipelining, out-ot-order execution, . Imprecise: system software has to figure out what is wher 。

54、e and put it all back together Performance goals often lead designers to forsake precise interrupts system software developers, user, markets etc., usually wish they had not done this,Multicycle Design-72,Handling Exceptions in Our Design,Consider two types of exceptions:undefined instruction & arit 。

55、hmetic overflow Basic actions on exception: Save state: save the address of the offending instruction in the exception program counter (EPC) Transfer control to OS at some specified address= need to know the cause for the exception= then know the address of exception handler After service, OS can te 。

56、rminate the program or continue its execution, using EPC to return,Multicycle Design-73,Push it onto the stack Vax, 68k, 80 x86 Save it in special registers MIPS EPC, BadVaddr, Status, Cause Shadow Registers M88k Save state in a shadow of the internal pipeline registers,Saving State: General Approac 。

57、hes,Multicycle Design-74,iv_base,cause,handler entry code,Traditional approach: interrupt vector The cause of exception is a vectorgiving the address of the handler PC - MEM IV_base + cause | 00 68000, Vax, 80 x86, . . . RISC Handler Table PC - IV_base + cause | 0000 Saves state and jumps Sparc, PA, 。

58、 M88K, . . . MIPS approach: fixed entry use a status register (cause register)to hold a field to indicate the cause PC - EXC_addr,Addressing the Exception Handler,Multicycle Design-75,Datapath with Exception Handling,Fig. 5.39,Multicycle Design-76,Datapath with Exception Handling,Fig. 5.39,Multicycl 。

59、e Design-77,Additions for Our Design,EPC: reg. to hold address of affected inst. Cause: reg. to record cause of exception Assume LSB encodes the two possible exception sources: undefined instruction=0 and arithmetic overflow=1 Two control signals to write EPC (EPCWrite) and Cause (CauseWrite), and o 。

60、ne control signal (IntCause) to set LSB of Cause register Be able to write exception address into PC, assuming at C000 0000hex = needs a 4-way MUX to PC May undo PC = PC + 4 (PC = PC - 4), since want EPC to point to offending inst. (not its successor,Multicycle Design-78,Undefined instruction: detec 。

61、ted when no next state is defined from state 1 for the op value Handle this by defining the next state value for all op values other than lw, sw, 0 (R-type), jmp, and beq as a new state, “other” Arithmetic overflow: detected with the Overflow signal out of the ALU This signal is used in the modified 。

62、 FSM to specify an additional possible next state Note: challenge in designing control of a real machine is to handle different interactions between instructions and other exception-causing events such that control logic remains small and fast Complex interactions makes the control unit the most cha 。

63、llenging aspect of hardware design,Exception Detection,FSM with Exception Handling,Fig. 5.40,Multicycle Design-80,Specialize state diagrams easily captured by microsequencer simple increment and branch fields datapath control fields Control design reduces to microprogramming Exceptions are the hard。

64、part of control Need to find convenient place to detect exceptions and to branch to state or microinstruction that saves PC and invokes OS Harder with pipelined CPUs that support page faults on memory accesses, i.e., the instruction cannot complete AND you must restart program at exactly the instruction with the exception,Summary 。

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标题：CS4100|CS4100： 计算机结构( 四 )